1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for improving lithography printability for integrated circuits.
2. Related Art
Lithography, which allows selective removal portions of a thin film such as photoresist, is a key process used in the fabrication of integrated circuits. Specifically, a photomask with the desired geometric pattern is created. Then, a light source passes through the photomask to transfer the geometric pattern on the thin film, which covers a substrate. The portions of the thin film that received light through the photomask are chemically altered by the light so that later process steps can remove these portions of the thin film to expose selected portions of the substrate. The substrate is then further processed to create the features of the integrated circuit.
When the feature size of the integrated circuit were relatively large, lithography techniques could easily transfer the geometric pattern of the photomask to the thin film. However, due to advancement in other areas of semiconductor processing, optical constraints in lithography processes has become a limiting factor of the feature size of semiconductor devices. Advancement in lithography allows feature sizes to be smaller than the wavelength of light used in the lithography pattern. However, the geometric pattern of the photomask does not transfer cleanly to the thin film. For example, as illustrated in FIG. 1(a), a rectangle 115 in a photomask 110 may result in a peanut shape 125 on thin film 120. In general, lithography steppers are limited to a critical dimension CD that is equal to a process factor (K1) multiplied by the frequency of the light used by the stepper (λ) divided by the numerical aperture (NA) (as show in Equation EQ1).CD=(K1*λ)/NA  (EQ1)
Lithography technology in 2007 uses deep ultraviolet light, which has a wavelength of 193 nm. The numerical aperture NA has a upper limit of 0.85 which can be increased using immersion technology to about 1.3-1.4. Because, the light frequency and numerical aperture are physically limited lithography processes attempt to reduce critical dimensions by reducing process factor k1 using various resolution enhancement techniques (RET) to improve the geometric pattern on the thin film. For example, in optical proximity correction(OPC), portions of the geometric pattern is reshaped to compensate for the deformity from the lithography process. As illustrated in FIG. 1(b), a reshaped polygon 135 (based on rectangle 115 of FIG. 1(a) with enhanced corners and sides) in a photomask 130 results in a near rectangular shape 145 on thin film 140. Near rectangular shape 145 approximates rectangle 115 more closely than peanut shape 125. Thus, RET/OPC can be used to improve the quality of the geometric pattern produced on the thin film and thus provides a better process factor K1.
However, RET/OPC require very complicated design rules. In addition, design rule technology in general can not adequately describe the complicated constraints of RET/OPC. Thus, even if a design passes the design rules, the integrated circuit manufactured from the design may still have “hot spots”, i.e. areas which would cause failure of the integrated circuit. Thus, excessive design rules are created for use with RET/OPC techniques to minimize the chances of hot spots in the fabricated devices. The excessive design rules are likely to lead to false violations, which would greatly increase the design time required for integrated circuits to address all the false violations.
Alternatively, hot spot detection and correction may be delayed until after RET/OPC. However, the post RET/OPC hot spot detection and correction would require detailed information about the RET/OPC process that is used by each foundry. Furthermore, each new generation of RET/OPC techniques may require years of development. Thus, IC development and design typically occurs long before the RET/OPC techniques are certified. In addition, simulation required to perform the post RET/OPC hot spot detection and correction is extremely time consuming and can greatly delay the IC design. Hence there is a need for a method and apparatus for rapidly detecting potential hot spots (sensitive spots) in an IC design.